Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation

This paper presents an improved VLSI (Very Large Scale of Integration) architecture for real-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic, particularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude estimation. The standard CORDIC implementation suffers of a loss of accuracy when the magnitude of the input vector becomes small. Using a fast magnitude estimator before running the standard algorithm, a pre-processing magnification is implemented, shifting the input coordinates by a proper factor. The entire architecture does not use a multiplier, it uses only shift and add primitives as the original CORDIC, and it does not change the data path precision of the CORDIC core. A bit-true case study is presented showing a reduction of the maximum phase error from 414 LSB (angle error of 0.6355 rad) to 4 LSB (angle error of 0.0061 rad), with small overheads of complexity and speed. Implementation of the new architecture in 0.18 µm CMOS technology allows for real-time and low-power processing of CORDIC and arctangent, which are key functions in many embedded DSP systems. The proposed macrocell has been verified by integration in a system-on-chip, called SENSASIP (Sensor Application Specific Instruction-set Processor), for position sensor signal processing in automotive measurement application

Hard macrocells for DC/DC converter in automotive embedded mechatronic systems

A novel configurable DC/DC converter architecture, to be integrated as hard macrocell in automotive embedded systems, is proposed in the paper. It aims at realizing an intelligent voltage regulator. With respect to the state of the art, the challenge is the integration into an automotive-qualified chip of several advanced features like dithering of switching frequency, nested control loops with both current and voltage feedback, asynchronous hysteretic control for low power mode, slope control of the power FET gate driver, and diagnostic block against out-of-range current or voltage or temperature conditions. Moreover, the converter macrocell can be connected to the in-vehicle digital network, exchanging with the main vehicle control unit status/diagnostic flags and commands. The proposed design can be configured to work both in step-up and step-down modes, to face a very wide operating input voltage range from 2.5 to 60 V and absolute range from −0.3 to 70 V. The main target is regulating all voltages required in the emerging hybrid/electric vehicles where, besides the conventional 12 V DC bus, also a 48 V DC bus is present. The proposed design supports also digital configurability of the output regulated voltage, through a programmable divider, and of the coefficients of the proportional-integrative controller inside the nested control loops. Fabricated in 0.35 μm CMOS technology, experimental measurements prove that the IC can operate in harsh automotive environments since it meets stringent requirements in terms of electrostatic discharge (ESD) protection, operating temperature range, out-of-range current, or voltage condition

Fast approximations of activation functions in deep neural networks when using posit arithmetic

With increasing real-time constraints being put on the use of Deep Neural Networks (DNNs) by real-time scenarios, there is the need to review information representation. A very challenging path is to employ an encoding that allows a fast processing and hardware-friendly representation of information. Among the proposed alternatives to the IEEE 754 standard regarding floating point representation of real numbers, the recently introduced Posit format has been theoretically proven to be really promising in satisfying the mentioned requirements. However, with the absence of proper hardware support for this novel type, this evaluation can be conducted only through a software emulation. While waiting for the widespread availability of the Posit Processing Units (the equivalent of the Floating Point Unit (FPU)), we can already exploit the Posit representation and the currently available Arithmetic-Logic Unit (ALU) to speed up DNNs by manipulating the low-level bit string representations of Posits. As a first step, in this paper, we present new arithmetic properties of the Posit number system with a focus on the configuration with 0 exponent bits. In particular, we propose a new class of Posit operators called L1 operators, which consists of fast and approximated versions of existing arithmetic operations or functions (e.g., hyperbolic tangent (TANH) and extended linear unit (ELU)) only using integer arithmetic. These operators introduce very interesting properties and results: (i) faster evaluation than the exact counterpart with a negligible accuracy degradation; (ii) an efficient ALU emulation of a number of Posits operations; and (iii) the possibility to vectorize operations in Posits, using existing ALU vectorized operations (such as the scalable vector extension of ARM CPUs or advanced vector extensions on Intel CPUs). As a second step, we test the proposed activation function on Posit-based DNNs, showing how 16-bit down to 10-bit Posits represent an exact replacement for 32-bit floats while 8-bit Posits could be an interesting alternative to 32-bit floats since their performances are a bit lower but their high speed and low storage properties are very appealing (leading to a lower bandwidth demand and more cache-friendly code). Finally, we point out how small Posits (i.e., up to 14 bits long) are very interesting while PPUs become widespread, since Posit operations can be tabulated in a very efficient way (see details in the text)

Formal verification and co-simulation in the design of a synchronous motor control algorithm

Mechatronic systems are a class of cyber-physical systems, whose increasing complexity makes their validation and verification more and more difficult, while their requirements become more challenging. This paper introduces a development method based on model-based design, co-simulation and formal verification. The objective of this paper is to show the applicability of the method in an industrial setting. An application case study comes from the field of precision servo-motors, where formal verification has been used to find acceptable intervals of values for design parameters of the motor controller, which have been further explored using co-simulation to find optimal values. The reported results show that the method has been applied successfully to the case study, augmenting the current model-driven development processes by formal verification of stability, formal identification of acceptable parameter ranges, and automatic design-space exploration

Performance evaluation of attribute-based encryption in automotive embedded platform for secure software over-the-air update

This paper aims to show that it is possible to improve security for over the air update functionalities in an automotive scenario through the use of a cryptographic scheme, called “Attribute-Based-Encryption” (ABE), which grants confidentiality to the software/firmware update done Over The Air (OTA). We demonstrate that ABE is seamlessly integrable into the state of the art solutions regarding the OTA update by showing that the overhead of the ABE integration in terms of computation time and its storage is negligible w.r.t. the other overheads that are introduced by the OTA process, also proving that security can be enhanced with a minimum cost. In order to support our claim, we report the experimental results of an implementation of the proposed ABE OTA technique on a Xilinx ZCU102 evaluation board, which is an automotive-oriented HW/SW platform that is equipped with a Zynq UltraScale+ MPSoC chip that is representative of the computing capability of real automotive Electronic Control Units (ECUs)

An instrument for the characterization and calibration of optical sensors

This paper presents the development of a hardware/software system for the characterization of the electronic response of optical (camera) sensors such as matrix and linear color and monochrome Charge Coupled Device (CCD) or Complementary Metal Oxide Semiconductor (CMOS). The electronic response of a sensor is required for inspection purposes. It also allows the design and calibration of the integrating device to achieve the desired performance. The proposed instrument equipment fulfills the most recent European Machine Vision Association (EMVA) 1288 standard ver. 3.1: The spatial non uniformity of the illumination ΔE must be under 3%, and the sensor must achieve an f-number of 8.0 concerning the light source. The following main innovations have achieved this: An Ulbricht sphere providing a uniform light distribution (irradiation) of 99.54%; an innovative illuminator with proper positioning of color Light Emitting Diodes (LEDs) and control electronics; and a flexible C# program to analyze the sensor parameters, namely Quantum Efficiency, Overall System Gain, Temporal Dark Noise, Dark Signal Non Uniformity (DSNU1288), Photo Response Non-Uniformity (PRNU1288), Maximum achievable Signal to Noise Ratio (SNRmax), Absolute sensitivity threshold, Saturation Capacity, Dynamic Range, and Dark Current. This new instrument has allowed a camera manufacturer to design, integrate, and inspect numerous devices and camera models (Necta, Celera, and Aria)

A multi-processor NoC-based architecture for real-time image/video enhancement

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